This Research-Team is a follow-up of A3 Research-Team
Project-Team Presentation
Joint project-team with the University of Paris-Sud 11 and CNRS (LRI), Located in Orsay.
The general research topic of the ALCHEMY project-team are architectures, languages and compilers for high-performance embedded and general-purpose processors. ALCHEMY investigates alternative solutions to incremental architecture and compiler optimizations for high-performance general-purpose and embedded processors. The increasing complexity of high-performance processor architectures has two main consequences. (1) In the short term, the inability to embed a sufficiently accurate architecture model in compilers makes it increasingly hard to generate efficient program optimizations, and thus to achieve high sustained performance. (2) In the long term, the architecture complexity makes it increasingly hard to scale processor architectures, more exactly to translate technology improvements into higher sustained performance. We are developping two approaches respectively corresponding to the short-term and long-term issues outlined above.
ALCHEMY stands for Architectures, Languages and Compilers to Harness the End of Moore Years, meaning both the complex but traditional processor architectures implemented using the current photolithographic processes, and novel architecture/language paradigms compatible with future and alternative technologies.
Research themes
Iterative compilation
For the short term, we are investigating program optimization techniques relying on dynamical analysis, i.e., the detailed analysis of the program behavior on the architecture during execution. Such techniques are usually called dynamic or iterative compilation. We are about to disseminate this research effort through an iterative compilation environment as part of the Center for Program Tuning that we are currently setting up.
Combined language/architecture approach
For the long term, we consider that both excessive processor architecture complexity and low sustained performance are rooted in the current architecture/programming model itself. More precisely, the current model fails in two ways: passing enough program semantics to the compiler and the architecture, and efficiently managing the increasing chip space brought by technology. For that purpose, we are investigating combined architecture/language approaches that can meet the two abovementioned properties. We are investigating languages that can pass the necessary semantic to the architecture and the compiler without sacrificing the ease of programming. As a result of the richer semantic, both the architecture and the compiler are simpler and potentially more effective. Moreover, we are investigating simple and regular architectures with self-organizing properties that can thus scale easily with technology. This long-term research work is strongly tied to technology issues, and for that reason, we are studying in parallel alternatives to current photolithographic silicon-based processes and their potential impact on architecture and programming paradigms.
Transversal methodology activity
For both approaches, we are also conducting a transversal methodology activity to develop processor simulators used for both program optimization and architecture purposes. This activity focuses on fast development and execution methods for processor simulators.
International and industrial relations
RNTL ATLAS (EADS, CEA)
RNTL COP (HP, STMicroelectronics)
RTP Architecture-Compilation
AIR&D joint virtual laboratory for Ambient Intelligence
Industry: HP France & HP Labs, Philips Research, STMicroelectronics
France: Univ. Paris 6, Univ. Toulouse, Univ. Versailles, CEA LIST, INRIA Compose, INRIA Compsys
International: Univ. Passau, UPC, Univ. Illinois
Scientific leader
Olivier TEMAM
[homepage]
+33 1 72 92 59 52
Olivier.Temam@lri.fr
Secretary : +33 1 72 92 59 18
Team Address
Parc Club Orsay Université, ZAC des vignes,
4 rue Jacques Monod - Bât G,
91893 Orsay Cedex France
