DART : Contributions of the Data Parallelism to Real Time (project-team)

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Project-Team Presentation

Joint project-team with LIFL (CNRS and Lille University - USTL), located in Lille.

These last few years, our research activities mainly concern data parallel models and compilation techniques. Intensive Signal Processing (ISP) with real time constraints is a particular domain that could benefit from this background. Our project covers the following new trend: a data parallel paradigm for ISP applications. These applications are mostly developed on embedded systems with high performance processing units like DSP or SIMD processors. We focus on multi processor architectures on a single chip (System-on-Chip, SoC). To reduce the ``time to market'', the DART project-team proposes a high level modeling environment for software and hardware design. This level of abstraction already allows the use of verification techniques before any prototyping. This also permits to produce automaticaly a mapping and a schedule of the application onto the architecture with code generation.

Research themes

The DART project-team contributes to this research field by the three following items:

• Co-modeling for SoC design:

  We define our own metamodels to specify application, architecture, and (software hardware) association. These metamodels present new characteristics as high level data parallel constructions, iterative dependency expression, data flow and control flow mixing, hierarchical and repetitive application and architecture models. All these metamodels are implemented with UML profiles in respect to the MOF specifications.

• Optimization techniques:

  We develop automatic transformations of data parallel constructions. They are used to map and to schedule an application on a particular architecture. This architecture is by nature heterogeneous and appropriate techniques used in the high performance community can be adapted. New heuristics to minimize the power consumption are developed. This new objective implies to specify multi criteria optimization techniques to achieve the mapping and the scheduling.

• SoC simulation:

  The data flow philosophy of our metamodel is particularly well suited to a distributed simulation. We have developed a more general distributed environment to support the execution of Kahn Process Networks. This kind of simulation is at the functional level. To take care of the architecture model and the mapping of the application on it, we propose to use the SystemC platform to simulate at different levels of abstraction the result of the SoC design. This simulation allows to verify the adequacy of the mapping and the schedule (communication delay, load balancing, memory allocation...). We also support IP integration with different levels of specification (functional, timed functional, transaction and cycle accurate byte accurate levels).

International and industrial relations

• We are members of two European ITEA projects.
  • Sophocles (System level develOpment Platform based on HeterOgeneous models and Concurrent LanguagEs for System applications implementation)

    Partners: THALES Communications, THALES Underwater Systems, Esterel Technologies, LIFL, Philips, IPiTEC and ENEA.

  • Prompt2Implementation (Parallel processing dedicated, Rapid Optimised Mapping Platform for Telecom applications to Implementation)

    Partners: Esterel Technologies, THALES Communications, INRIA (Sosso), LIFL, Nokia, University of Technology of Tampere and University of Turku.

• We participate with THALES and the CEA to the Protes project of the Carroll partnership.
• We codirect a PhD thesis with Prosilog SA.
• We have a partnership with the Center of Embedded Computer Systems, University of California around the cosimulation of SpecC and SystemC.
• We participate to the RNRT SoCLib platform project with the CEA, the CNRS, Thales Communications, ST Microelectronics, Prosilog and TurboConcept.
• Finally, we contribute to EuroSoC, ex Network of Excellence that is still active though the Europe does not support it.

Scientific leader

Jean-Luc DEKEYSER     [homepage] (in french)
+33 3 59 57 78 04
dekeyser@lifl.fr
Secretary : +33 3 59 57 78 30

Team Address

Parc Scientifique de la Haute Borne
Park Plaza Bât A 40 avenue Halley
59650 VILLENEUVE D ASCQ